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About the differences between the TTL* families

First there was normal TTL* (Transistor Transistor Logic). There were also things like DTL (Diode Transistor Logic).

TTL* became very popular, very soon, although CMOS* was also already used by many other people.
CMOS* and TTL* were quite different in handling and levels. CMOS* was 3V to 15V. TTL* was 4.75V to 5.25V. CMOS* used much less energy because it was high-impedance.
In CMOS* every connection between the power lines, always has two transistors in it's path of which one is always closed.

Comment by Ian Cox of the UK:

CMOS* doesn't have NPN & PNP transistors but CMOS* N-channel and P-Channel FETS and it is actually in CMOS* that BOTH devices turn on and short out the supply for micro-moment during switching. I am not aware of this phonomenom in TTL* logic (even old stuff).

CMOS* was much more sensitive to static electricity.

After a while LS* (Low Power Schottky) TTL* was invented, probably by Schottky. It used much less energy and was as fast as normal TTL*.
Everybody started using LS*. (Except for the fast versions: S and FACT and FAST.)
These chips were for example used for a single critical chip on a board, like a (primitive) MMU* which would otherwise slow down the memory access to much.

TTL* with it's higher power usage, had always been faster than CMOS*. Therefore CMOS* was more used for analogue and TTL* for digital circuits, but after some time, they invented HC (High speed CMOS*) and made (High speed CMOS*, TTL-compatible) with it.
This means, that internally a HCT* chip is completely High speed CMOS* and at the in and outputs are converters, that convert the levels to TTL*.

Comment by Ian Cox of the UK:

You advise the use of HC, but AC (Advanced CMOS*) or ACT (same again but it's input levels have been doctored to be compatible with old-fashioned TTL*) has higher current drive capability (24mA!) and is generally faster still!

HCT* is mostly compatible with TTL*, except:

• You should never leave an input open, because the circuit can start to oscillate, which costs a lot of energy and can disturb the working of the rest of the circuit.
• You can't use the 74HCT04 as an oscillator (with a crystal), as was often done. But they designed a special version of the 74HCT04 for this: The 74HCU04!

Conclusion:

• Normally use HCT*.
• If you want faster chips, use FACT/FAST or whatever.
• You can replace TTL-chips on old boards generally with HCT*, unless it's an 7404 near a crystal or the designer of the board relies on the (slow) speed of certain components, which he should never have done!

What is the difference between the 54 and 74 family?

Is the power supply of CMOS* only 5V?

In earlier days, chips needed all kinds of weird voltages. Now they generate their own (low current) voltage internally by way of a charge pump, if necessary.

Why would you mix TTL* and CMOS* devices?

Why did TTL-to-CMOS and CMOS-to-TTL require interfacing devices

Currently even 'TTL*' is done in CMOS*. HCT* means 'High speed CMOS* TTL* compatible'.

What is ECL*?

J.R. "Zeke" Walton from NASA.

What is BiCMOS?

What to use in the daily practice?

Additional question

From:    ganswijk@xs4all.nl
To:      Chipdir Mailing List
Subject: Re: Two Queries

I have written a page about it:
http://www.chipdir.com/chipdir/ttl.htm

The generations of the most economical types were:

These are basically compatible but every generation is faster than the last and uses much less energy. HCT* is CMOS*, so you need to connect all the inputs which was not needed with parts of the other generations. Also the 74ls04 that was often used in an oscillator circuit couldn't be replaced by the 74HCT04, but they produce a special version, the 74HCU04 that can be used in this special way.

All other types of 74 chips were faster or used less energy or whatever. They would have been more expensive, but if that is no problem I don't see a reason not to use them as drop-in replacements.

Beware that the 74HC's may be real CMOS* and not TTL* compatible as the HCT* (=High Speed CMOS* TTL* compatible). HCT* is CMOS* that has been made to act as TTL*, so 0 and 5V power and probably levels of 0.8 and 2.7 V for low and high.

When a design is really critical I'd check the datasheets, but I'd even do that with HCT*...

Example

By the way, we have built such a 6809 Unix computer around 1984 and used a couple of them for many years since then, both for database, accounting and embedded software writing. We never built a successor both because it was hard to find a good 16/32 bits processor and because the 80286 was already then a viable similarly functional system with MMU on-board and could run Xenix quite well. With the arrival of the 80386 there was absolutely no incentive to build our own computers anymore. Motherboards were getting cheaper and cheaper. Xenix was still expensive though. Linux changed this of course. MS Windows also became more and more a serious platform.

Overview

CMOS* Technology:

74C	CMOS*	Uses CMOS* transistors and hence has switching levels set at half supply unlike all of the above. These can usually be run of supplies from about 3 to 15V.
74AC	High speed TTL* I/O
74ACT	High speed TTL*/CMOS* Input CMOS* Output
74FC	High speed TTL*/CMOS* Input CMOS* Output
74HC	High speed CMOS*	Faster using CMOS* transistors, half supply switching. 5v only.
74HCT*	High speed CMOS* with TTL* switching levels	Uses CMOS* but designed to switch at TTL* levels (ie low = <0.6V, high = >2V)
74AHC	Advanced HC?	Faster than HC?
74AHCT	Advanced HCT*?	Faster than AHCT?

More subtle differences

1. Can anyone point me to a reference that tells me the difference between all the 74xx series logic families? I am finding it difficult to get some 7400 series chips locally, like today I had problems with the 74LS01. I need to know could I shove in a 74ALS01, or 74F01, or 74L01. What is the difference between 74HC and 74HCT*...that sort of thing.

There are many subtle differences that might come into play when you go between families. Depends on your circuits.

In my opinion, the major differences from the user's perspective, are speed, and input thresholds. Some CMOS* families use optimized "CMOS*" levels while others use "TTL*" or perhaps "LVTTL" levels. TTL*'s input threshold is around 1.4V, versus 2.5V (Vdd*/2) for 5V-CMOS. TTL* accepts 2.0V as "high"; CMOS* would call this marginally "low" and needs a much higher voltage to be considered "high".

But when you come down to using them in your circuits, you also need to think about things like:

• Input current , in both high and low states. If you substitute a 74HCT* with a 74F, the current (i.e., loading) is a lot higher.
• Output drive capability.
• Output drive symmetry. Is it suitable for driving long bus wires, or will pulsewidths suffer?
• Signal integrity. Faster gates make faster output edges. 74F is fast, but watch it if you need to drive more than a few inches (depending on what it drives).
• Power dissipation, if you have a lot of them.
• Clamping at inputs, I/Os*, and tri-state outputs. If you use a 3.3V family, will it clamp above 3.3V, or is it 5V-tolerant? You can get both.
• Can unused inputs float? Some are OK with that, others aren't.
• Noise immunity. Faster gates will see noise glitches on their inputs that slower gates miss.

Get as many data books as you can and study them until you familiarize yourself with all these differences. What may be an acceptable substitute in one case, may be a flop in another.

Regards,
Andy

See also

Difference between 54 and 74 family

The specs for 54xx usually show them as being slower than 74xx, although in fact this is probably just a derating for the extended temp range.

ECL*

(Read this in the voice of Grandpa Simpson:)

Back in the 70's, you had 7400 and 74S00. Maybe you were just getting 74LS00. If you wanted things to run at, say, 300 MHz, you could do it with ECL*. ECL* logic uses a -5.2 V supply, and switches above and below a certain threshold voltage, I think it's -1.2V. A lot of the devices had + and - outputs for the same function, or differential inputs. You could apply + and - ECL* outputs to a twisted pair cable, run it a few feet to a different board, and apply the cable to a differential ECL* input, and it would work at very high speeds. Since it switches current from one side to the other, rather than turning it on and off, and since the voltage swings are very small, ECL* had far less noise problems than TTL* and would run at high speeds on wire-wrapped boards. You needed to use terminating resistors on every signal, though. Lots of power.

I encountered stuff like this inside a 70's era Control Data disk drive. This thing had a 60 MB removable pack about 12" in dia and 6" thick. The entire unit was about the size of a modern office photocopier, and weighed more. The backplane was connected with wire-wrap. The termination resistors in the interface cable used more power than an entire modern HDD.

ECL* is not really used any more.

74H00 - higher power, faster than 7400
74L00 - low power, slower than 7400.
These were used before 74S and 74LS*, and were a direct power/speed tradeoff. They were already obsolete in the late 70's when I started tinkering with this stuff.

ECL*, reaction

Regarding the comment about ECL* not being much use for anything.

ECL* was quite important in the 1970s, 1980s and early 1990s. It was used for very high speed circuits. Early supercomputers e.g. Cray's were made with it. However, it was very power hungry. I think that it isn't much used nowadays. If you try to use any old ECL* chips, the logic levels are typically around 0.9V below VCC for logic high and 1.8V below supply for logic low. Supply is generally 0V and -5V, rather than 5V and 0V.

Propagation

From:    Jaap van Ganswijk <ganswijk@xs4all.nl>
To:      Silver Timothy (eeb2_99) <silvert@ee.port.ac.uk>
Subject: Re: LS* TTL* logic family

I am a student at portsmouth university and I am having trouble
understanding this topic. Could you possibly enlighten me about;
"Typical gate propagation delays for the LS* TTL* logic family"?

It means transmission in this case and the propagation time or propagation delay is the time in which a signal travels through a gate. It's typically 4 ns for LS* TTL*, I think. A simple NAND* consists of a single gate. An AND* of two gates and for example a 74LS138 has usually several gates from input to output so it takes say 6 times 4 ns.

In serious PCB-designs you need to calculate how long it takes for signals to go from serious chip A to serious chip B through all the intermediate TTL-chips. If the signal takes too long the circuit may start to behave badly (at first at higher temperatures etc.)

First you try to calculate everything exactly and then at an extra proof you can put the finished product in an oven and heat it up to check if it still works. This will give a clear indication of how reliable it is.

Some more info ...

Joe da Silva

Z-state (high impedance)

Can you tell me the meaning of the term z-state(High impedance) for a digital circuit and how do all the logic families implement this?

A digital output is internally usually connected with one transistor to the 5V and one transistor to the 0V. Only one of those is normally conducting electrical current at a certain moment pulling the output pin either to the 0V or the 5V. When none of the two transistors is conducting, the output is in the Z-state (high impedance state).

The different logic families use different technology to implement the transistors, but the principle is probably the same.

Buy the way early chips were made in a technique whereby both of the transistors would conduct current for a short time during transitions. This made them actually short the 5V to the 0V for a very short time. Therefore these parts would use a lot of energy and become very hot. DRAM* from around the time that about 16kbit per chip was producable could easily burn your finger so feeling the chip to debug the hardware was not and advisable idea. You should at least wet your finger first. If you like to repair old computers like the TRS-80, Apple2, Commodore PET, BBC etc. it's wise to remember this...

Open inputs

In the TTT, CMOS* page (ttl*.htm) you mention not leaving CMOS* inputs floating, but should they be tied to ground or Vcc*, or doesn't it matter which?

Specifically at this time I'm looking at a 74HC14 hex* inverter, but would also like to know if there's a rule of thumb to follow i.e. drive inputs such that the output is always high, or low, or either of the two is OK.

It's not easy to determine what the optimal solution is.

The problem with CMOS* inputs is that they are very high impedance and may pick up signals from the surrounding environment and the air and may start to oscillate. This may not only cause highly increased power usage but also other undesired effects.

So as long as you tie the inputs to a signal with well defined value at each point of time, like a neighboring data pin, either in- or output or 0V or 5V this problem will be prevented. For some technologies it seems to be recommended to connect the 5V via a relatively low-R resistor (4k7 for example). Power inputs of a chip can normally withstand a power surge, but inputs may not.

What the optimal solution is depends on all kinds of factors: Does the technology draw more current with a low or high input?
When connecting the input to a neighboring pin, you'll have to consider the load on the given signal. But all this is in most cases not very important. It's only relevant when for example battery life must optimal or signal speed is crucial. In practical cases I'd just solder it to the 0V or 5V if any is available on the next pin, or in case of a two-input (N)AND* or (N)OR* which is just used as an invertor, I'd solder both inputs together or otherwise it depends on which signals are available closeby and if they can drive an extra load (which they usually can) and if their reaction speed isn't crucial for the system (which it usally isn't).

In case of your hex* invertor you could consider feeding certain signals to two invertors parallel to each other and also tying the outputs together. It will double the load on the input signal, but will also double the drive of the output signal. It might however increase the power usage during the moment of switching when the two gates should have significantly different switching times, but that is of course very unlikely. ;-)

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