| nr |
name |
description |
manufacturer |
|
ADSST-AEC |
Fixed Point DSP* Acoustic Echo Cancellation (AEC) algorithm chipset |
AD |
|
ADSST-AEC-SPA |
Fixed Point DSP* Acoustic Echo Cancellation (AEC) algorithm chipset from Signal Processing Associates |
AD |
|
ADSST-AGC |
Fixed Point DSP* Digital Automatic Gain Control algorithm chipset from Signal Processing Associates |
AD |
|
ADSST-AUD-DD |
SHARC* Floating Point DSP-based Dolby Digital chipset |
AD |
|
ADSST-AUD-HDCD |
SHARC* Floating Point DSP* with HDCD Decoder/Post Processing Filter algorithm chipset |
AD |
|
ADSST-AUD-MPEG |
SHARC* DSP* MPEG II Audio Decode algorithm chipset |
AD |
|
ADSST-AUD-THX |
SHARC* Floating Point DSP* THX Decode algorithm chipset |
AD |
|
ADSST-AUD_PROL |
SHARC* Floating Point DSP* Dolby Pro-Logic algorithm chipset |
AD |
|
ADSST-CID |
Fixed Point DSP* Caller Identification algorithm chipset |
AD |
|
ADSST-CS |
Extended Csound Development Environment |
AD |
|
ADSST-DAM |
Fixed Point DSP* Digital Answering Machine Application and Reference Design |
AD |
|
ADSST-DTMF |
Fixed Point DSP* DTMF Decode and DTMF Encode algorithm chipset |
AD |
|
ADSST-LEC |
Fixed Point DSP* LEC algorithm chipset |
AD |
|
ADSST-MGSM |
Fixed Point DSP* MGSM Speech Code, 5.0 Kbps algorithm chipset |
AD |
|
ADSST-MPEG |
Fixed Point DSP* MPEG Audio I algorithm chipset |
AD |
|
ADSST-TONE_DET |
Fixed Point DSP* Tone Detection algorithm chipset |
AD |
|
ADSST-VAD |
Fixed Point DSP* Voice Activity Detection algorithm chipset |
AD |
|
ADSST-VOICDIAL |
Fixed Point DSP* Voice Dialer algorithm chipset |
AD |
|
MWave |
One of the first DSP* architectures, Family |
IBM* |
|
SHARC* |
DSP*, Family |
AD* |
| 1 |
ADSST-METER-1 |
Fixed Point DSP* Energy Meter Reference Design and Chipset, data |
AD |
| 100 |
ADSST-DT-100 |
Fixed Point DSP* Digital Telephony Development Board, data |
AD |
| 14060 |
AD14060 |
AD14060/AD14060L Quad-SHARC TM DSP* Multiprocessor family, data |
AD |
| 14060 |
AD14060L |
AD14060/AD14060L Quad-SHARC TM DSP* Multiprocessor family, data |
AD |
| 14160 |
AD14160 |
Quad-SHARC 5V Multi-Chip Module, data |
AD |
| 14160 |
AD14160L |
Quad-SHARC DSP* in Ceramic Ball Grid Array, data |
AD |
| 21 |
21XX-EZLITE |
ADSP-2100 family Fixed-Point Development Tools, data |
AD |
| 210 |
210XX-EZLITE |
ADSP-21000 family Development Tools, data |
AD |
| 2100 |
|
DSP* |
AD* |
| 2100 |
ADSST-NAV-2100 |
Fixed Point DSP* GPS Receiver algorithm chipset, data |
AD |
| 21000 |
|
DSP* family (?) |
AD* |
| 21000 |
21000-HARDWARE |
SHARC* EZ-KIT LITE, data |
AD |
| 2101 |
ADSP-2101 |
16-bit, 25 MIPS, 5v, 2 serial ports, data |
AD |
| 21020 |
|
Floating-Point DSP* MPU |
AD* |
| 2103 |
ADSP-2103 |
16-bit, 10.2 MIPS, 3.3v, 2 serial ports, data |
AD |
| 2104 |
ADSP-2104 |
16-bit, 20 MIPS, 5v, 2 serial ports, data |
AD |
| 2104 |
ADSP-2104L |
16-bit, 13 MIPS, 3.3v, 2 serial ports, data |
AD |
| 2105 |
ADSP-2105 |
16-bit, 20 MIPS, 5v, 2 serial ports, data |
AD |
| 21060 |
ADSP-21060 |
SHARC*, CMOS*, 120 MFLOPS*, floating point, data |
AD |
| 21060 |
ADSP-21060L |
SHARC*, CMOS*, 120 MFLOPS*, 3.3 v, floating point, data |
AD |
| 21061 |
ADSP-21061 |
Low-cost SHARC*, 150 MFLOPS*, 5v, floating point, data |
AD |
| 21061 |
ADSP-21061L |
Low-cost SHARC*, 150 MFLOPS*, 3.3v, floating point, data |
AD |
| 21062 |
ADSP-21062 |
SHARC*, 40 MIPS, 5 v, 120 MFLOPS*, floating point, data |
AD |
| 21062 |
ADSP-21062L |
SHARC*, 40 MIPS, 3.3 v, 120 MFLOPS*, floating point, data |
AD |
| 21065 |
ADSP-21065L |
Low-cost SHARC*, 180 MFLOPS*, 3.3v, data |
AD |
| 2115 |
ADSP-2115 |
16-bit, 25 MIPS, 5v, 2 serial ports, data |
AD |
| 21160 |
ADSP-21160M |
SHARC*, 100 MHz, 600 MFLOPS*, 3.3v I/O, 2.5v core, data |
AD |
| 2150 |
|
DSP* Microcomputer |
AD* |
| 2155 |
|
DSP* Microcomputer |
AD* |
| 2156 |
|
DSP* Microcomputer |
AD* |
| 2158 |
ADSP-21msp58 |
Fully-integrated, single-chip DSP*, data |
AD |
| 2159 |
ADSP-21MSP59 |
Fully integrated, single-chip DSP* complete with a high performance analog front end, data |
AD |
| 2171 |
ADSP-2171 |
16-bit, 33 MIPS, 5v, 2 serial ports, host port, data |
AD |
| 2173 |
ADSP-2173 |
16-bit, 20 MIPS, 3.3v, 2 serial ports, host port, data |
AD |
| 2181 |
ADSP-2181 |
16-bit, 40 MIPS, 5v, 2 serial ports, host port, 80 KB RAM, data |
AD |
| 2183 |
ADSP-2183 |
16-bit, 52 MIPS, 3.3 v, 2 serial ports, host port, 80 KB RAM, data |
AD |
| 2185 |
ADSP-2185 |
16-bit, 40 MIPS, 5 v, 2 serial ports, host port, 80 KB RAM, data |
AD |
| 2185 |
ADSP-2185L |
16-bit, 52 MIPS, 3.3v, 2 serial ports, host port, 80 KB RAM, data |
AD |
| 2186 |
ADSP-2186 |
16-bit, 40 MIPS, 5v, 2 serial ports, host port, 40 KB RAM, data |
AD |
| 2186 |
ADSP-2186L |
16-bit, 40 MIPS, 3.3 v, 2 serial ports, host port, 40 KB RAM, data |
AD |
| 2187 |
ADSP-2187L |
16-bit, 52 MIPS, 3.3v, 2 serial ports, host port, 160 KB RAM, data |
AD |
| 236 |
A236 |
Video DSP*, parallel video digital signal processor chip is directly programmable in C, performs 160 million MACS and 320 million pixels/s for motion estimation, www.oxfordmicrodevices.com/a236-sum.html |
Oxford* |
| 263 |
ADSST-H.263 |
H.263 Video Compression/Decompression algorithm chipset, data |
AD |
| 2780 |
DSP2780 |
IBM's MWave DSP*, Family |
IBM* |
| 3001 |
NC3001 |
32-processor parallel DSP*, www.neuricam.com/ |
NeuriCam* |
| 3002 |
NC3002 |
32-processor parallel DSP*, www.neuricam.com/ |
NeuriCam* |
| 3003 |
NC3003 |
32-processor parallel DSP*, www.neuricam.com/ |
NeuriCam* |
| 32 |
ADSST-MOD-V32 |
Fixed Point DSP* V.32 Modem* algorithm chipset, data |
AD |
| 32010 |
TMS32010 |
16/32-Bit DSP*, 160 ns Instruction Cycle, 16*16=32-Bit Multiply |
TI* |
| 32010 |
TMS320C10NL |
dig sig proc 16/32 bit cmos |
TI |
| 32010 |
TMS320C10NL-14 |
dig sig proc 16/32 bit cmos 14mhz |
TI |
| 32011 |
|
16/32-Bit DSP*, 160 ns Instruction Cycle, 16*16=32-Bit Multiply |
TI* |
| 32015 |
|
16/32-Bit DSP*, 160 ns Instruction Cycle, 16*16=32-Bit Multiply |
TI* |
| 32017 |
|
16/32-Bit DSP*, 160 ns Instruction Cycle, 16*16=32-Bit Multiply |
TI* |
| 32020 |
|
16/32-Bit DSP*, 100 ns Instruction Cycle, 16*16=32-Bit Multiply |
TI* |
| 32025 |
|
16/32-Bit DSP*, 100 ns Instruction Cycle, 16*16=32-Bit Multiply |
TI* |
| 32025 |
TMS320C25GBL |
d.s.p. cmos 40mhz |
TI |
| 32030 |
|
32-Bit Floating Point DSP*, 60 ns Instr Cycle, 32*32=40-Bit Multiply |
TI* |
| 32040 |
|
32-Bit Floating Point DSP* |
TI* |
| 32044 |
|
32-Bit Floating Point DSP* |
TI* |
| 3206201 |
TMS320C6201B |
TMS320C6000 DSPs BREAK THE POWER BARRIER - LESS THAN 1.9 WATTS: The new TMS320C6201B demonstrates less than 1.9 Watts of typical power dissipation and is sampling today. The original 'C6201 is currently in volume production, with volume production for the lower power 'C6201B scheduled for 1Q99. |
TI* |
| 3206202 |
TMS320C6202 |
TWO NEW GROUNDBREAKING 'C62x DEVICES: TI has recently announced two new devices, the TMS320C6202 offering 2000 MIPS, www.ti.com/sc/c62xdsps |
TI* |
| 3206211 |
TMS320C6211 |
TWO NEW GROUNDBREAKING 'C62x DEVICES: TI has recently announced two new devices, the TMS320C6211 offering 1200 MIPS for $25 (in 25K unit quantities), www.ti.com/sc/c62xdsps |
TI* |
| 3206701 |
TMS320C6701 |
THE WORLD'S HIGHEST PERFORMANCE FLOATING-POINT DSP* - TMS320C6701 SHIPPING NOW: TMS320C6701 sample silicon is available today providing the highest floating point performance available and is pin-for-pin compatible with the fixed-point 'C6201/'C6201B in a 35mm BGA package. 'C6701 silicon was demonstrated last week at DSP* World. Volume production for the 'C6701 is scheduled for 2Q99. |
TI* |
| 3210 |
|
DSP*?, Same as TMS32010? |
AT&T |
| 324 |
ADSST-VC-H324 |
Videophone Reference Design, data |
AD |
| 34 |
ADSST-MOD-V.34 |
Fixed Point DSP* V.34 Modem* algorithm chipset, data |
AD |
| 382780 |
IBM38MDSP2780 |
IBM's MWave DSP*, Family |
IBM* |
| 436 |
A436 |
Video DSP*, parallel video digital signal processor chip is directly programmable in C, performs 3 billion MACS and 6 billion pixels/s for motion estimation, provides a fully software programmable universal video compressor/decompressor, www.oxfordmicrodevices.com/A436_summary.html |
Oxford* |
| 56000 |
|
24-bit digital signal processor family |
Motorola* |
| 56002 |
|
DSP* object code compatible with 56000, different pin layout, also 3.3V version |
Motorola |
| 56156 |
DSP56156 |
Motorola univ. DSP* 16 bits 20 mips* |
order from Barend |
| 61810 |
|
DSP* |
Hitachi* |
| 61811 |
|
DSP* RAM |
Hitachi* |
| 6403 |
NM6403 |
Russian DSP*. See here |
Module |
| 6620 |
AD6620 |
65MSPS Digital Receive Signal Processor, data |
AD |
| 723 |
ADSST-G723 |
SHARC* Floating Point DSP* G.723.1 algorithm chipset, data |
AD |
| 723 |
ADSST-G723-SPA |
Fixed Point DSP* G.723.1 algorithm chipset from Signal Processing Associates, data |
AD |
| 723 |
ADSST-SH_G723 |
Floating Point DSP* G.723.1 algorithm chipset, data |
AD |
| 728 |
ADSST-G728 |
Fixed Point DSP* G.728 algorithm chipset from Signal Processing Associates, data |
AD |
| 729 |
ADSST-G729-SPA |
Fixed Point DSP* G.729 algorithm chipset from Signal Processing Associates, data |
AD |
| 729 |
ADSST-G729A |
G.729a Algorithm Chipset, data |
AD |
| 729 |
ADSST-G729ASPA |
Fixed Point DSP* G.729a algorithm chipset from Signal Processing Associates, data |
AD |
| 7720 |
|
Programmable DSP*, pinout |
NEC* |
| 7730 |
|
Dedicated DSP* (ADPCM* convertor), pinout, Regs |
NEC* |
| 817820 |
|
Digital Signal Processor Enhance ZTAT |
Hitachi* |
| 81810 |
|
Digital Signal Processor Wide Temperature Range |
Hitachi* |
| 81820 |
|
Digital Signal Processor Enhance |
Hitachi* |
| 81831 |
|
Digital Signal Processor Image |
Hitachi* |
| 8695 |
Z8695 |
Z8 DSP* Desc, Card |
Zilog* |
| 8900 |
|
16-bit DSP* Desc |
Zilog* |
| 89120 |
|
16-bit CPU+DSP* (mixed signal processor), with ROM, Desc |
Zilog* |
| 89121 |
|
16-bit CPU+DSP* (mixed signal processor), with ROM, Desc |
Zilog* |
| 89320 |
|
16-bit mixed signal processor, Desc |
Zilog* |
| 89321 |
|
16-bit DSP*, Desc |
Zilog* |
| 89371 |
|
16-bit DSP*, Desc |
Zilog* |
| 89920 |
|
16-bit CPU+DSP* (mixed signal processor), ROM-less, Desc |
Zilog* |
| 89921 |
|
16-bit CPU+DSP* (mixed signal processor), ROM-less, Desc |
Zilog* |
| 9124 |
LH9124 |
500 MOPS FFT* vector processing DSP* more |
| 96000 |
|
32-bit digital signal processor family |
Motorola* |
| 9802 |
AD9802 |
A Complete CCD* Signal Processor Developed For Electronic Cameras, data |
AD |
| 9805 |
AD9805 |
Complete 12-Bit /10-Bit 6 MSPS CCD*/CIS Signal Processors, data |
AD |
| 9807 |
AD9807 |
Complete 12-Bit /10-Bit 6 MSPS CCD*/CIS Signal Processors, data |
AD |
| 9816 |
AD9816 |
Complete, 12-Bit 6 MSPS CCD*/CIS Signal Processor, data |
AD |
